FIG. 1A shows a portion of a conventional NAND flash system. It generally comprises a NAND FLASH chip module (chip module) 102 coupled to a controller 120 through various signal lines and one or more data buses 104. The signal lines include chip enable lines (CE0 to CEN-1), a write enable line (WE#), a read enable line (RE#), an address latch enable (ALE) line, and a command latch enable (CLE) line. The data bus (I/O Data[0:7]) is an 8-bit bus for writing data into and reading it from the module. (Other signals, not necessarily required for understanding the invention, may not be shown.)
The NAND flash chip module 102 comprises N (e.g., 4, 20, or even more) individual NAND flash chips coupled together to provide increased memory space. Each chip has a separate chip enable input to be asserted when one or more of its cells is to be accessed. Accordingly, the system has the N separate chip enable signals (CE0 to CEN-1) coupled between the module 102 and controller 120 for selectably accessing the separate chips in the module.
A popular NAND flash interface is the Open NAND Flash Interface (ONFI) specification. The specification uses the CLE and ALE signals for writing an instruction (command code plus address) into the module. The CLE and ALE signals indicate to the module whether a command code or address portion will be coming over the data bus 104. The write and read enable signals, respectively, cause data on the bus to be written into the module or to be read from the module to the controller via the data bus 104.
FIG. 1B is a truth table showing the different operating modes for the ALE and CLE signals in the ONFI specification. When both signals are de-asserted (e.g., ‘0), the module is in a NOOP state, which is an allowed but inactive state. When the CLE is asserted and the ALE is de-asserted, the module is in a command mode, which signifies to the module that data to be written into it corresponds to a command instruction. On the other hand, when the ALE is asserted and the CLE is de-asserted, then the module is in an address mode, indicating to it that data to be written into it is address data.
FIG. 1C shows a timing diagram for the signal lines when an instruction is written to the module to execute a memory operation. Initially, the CLE line is asserted, indicating that a command byte will be coming from the bus. A command code (e.g., single byte, 8-bit) command code) is then placed by the controller 120 onto the bus. Next, the write enable signal (active low here) is strobed to write the command code into the module. Next, the CLE line de-asserts, and the ALE line asserts, indicating that the address for the command is coming. In the depicted embodiment, a 24-bit address is used, so three separate address bytes are strobed into the module while the ALE is asserted and CLE is de-asserted. From here, depending on the specified command, data is usually then read from or written to one or more cells, as specified by the address.
Having the ability to facilitate multiple chip enable signals increases the parallelism of operations and improves overall performance. Unfortunately, however, a relatively high number of chip enable lines can be costly in that it may require excessive routing and/or pin-outs. For example, in a solid-state NAND flash drive with ten packages (2 chips per package), 20 separate chip enable lines may be required.
Accordingly, a new approach is desired.